1. Technical Field
The present disclosure relates to the protection of an integrated circuit chip against laser attacks.
2. Discussion of the Related Art
Some integrated circuit chips may be the target of external attacks aiming at disturbing the normal operation of the integrated circuit or at obtaining protected confidential data. To intentionally cause disturbances in the circuits of a chip, an attack mode comprises bombarding chip areas with a laser beam while the chip is operating. Due to the presence of interconnection metal tracks on the front surface side of the chip, laser attacks are often carried out on the back side.
To avoid fraud, chips comprising attack detection devices have been provided. The attack detection device is coupled to a chip protection circuit. When an attack is detected, the protection circuit implements measures of protection, modification, or destruction of the critical data. For example, it may be provided, when an attack is detected, to interrupt the power supply of the chip or to cause its resetting, in order to reduce the time during which the attacker can study the chip response to a disturbance.
European patent EP2109139 describes an embodiment of an integrated circuit chip associated with a device for detecting a laser attack.
FIG. 1 is a partial simplified cross-section view of such an integrated circuit chip. The integrated circuit chip comprises P-type doped wells 2 and N-type doped wells 4 extending in the upper P-type doped portion of a substrate 1 of a semiconductor material, for example, a silicon epitaxial layer. Only a well 2 and a well 4 are shown. Wells 2 and 4 are laterally separated by an insulating region 5 formed in substrate 1. Each of wells 2, 4 may contain several components. As an example, a P-channel transistor T1 has been shown in well 4 and an N-type transistor T2, close to transistor T1, has been shown in well 2. Each transistor comprises a gate 7 of a conductive material, insulated from substrate 1 by a gate insulator 6, and doped source and drain regions 9 extending in substrate 1 on either side of gate 7. Source and drain regions 9 of P-channel transistor T1 are heavily P-type doped, and source and drain 9 of N-channel transistor T2 are heavily N-type doped.
A heavily-doped P-type contact region 12, extending at the surface of well 2, is intended to be directly connected to ground GND. A heavily-doped N-type contact region 24, extending at the surface of well 4, is intended to be connected to a source of voltage Vdd.
N-channel transistor T2 of well 2 is inverter-assembled with P-channel transistor T1 of well 4, that is, the gate of the N-channel transistor is connected to the gate of the P-channel transistor, forming input terminal IN of an inverter, and the drain of the N-channel transistor is connected to the drain of the P-channel transistor, forming output terminal OUT of the inverter. In operation, the source of the P-channel transistor is at high power supply voltage Vdd. The source of the N-channel transistor is at ground GND.
The chip comprises an N-type buried layer 16 extending in substrate 1 under wells 2, 4. Buried layer 16 is in contact with N-type well 4. An N-type region 18 extends in substrate 1 from the upper surface of the substrate all the way to buried layer 16. Region 18, with N-type well 4, totally surrounds P-type well 2. A heavily N-type doped contact region 19 extends at the surface of region 18. Contacts 24 and 19 are intended to bias N-type wells 4 and buried layer 16 to voltage Vdd. A heavily-doped P-type contact region 21, extending at the surface of substrate 1, is intended to be directly connected to ground GND. Contact 21 for example has the shape of a ring surrounding wells 2 and 4. Voltage Vdd is provided by a power supply source 26 associated with a detection circuit 28.
When a laser beam reaches the rear surface of the chip, buried layer 16 tends to capture electrons originating from electron/hole pairs photogenerated in the substrate. These electrons are attracted by the positive voltage applied on contacts 19 and 24, and cause parasitic signals which are detected by detection circuit 28.
An embodiment of power supply source 26 and of detection circuit 28 is described in detail in above-mentioned European patent EP2109139.
A disadvantage of the system for detecting a laser attack described in relation with FIG. 1 is due to the fact that noise induced by the normal operation of the chip components is present on contact 24 for biasing Vdd of well 4. This noise may be confounded with the parasitic signals resulting from a laser attack. Measures of protection, modification, or destruction of the confidential data of the chip may then be erroneously implemented, while a laser attacked has not occurred.
A system for a detecting a laser attack on an integrated circuit chip is thus needed, the detection system being unlikely to be disturbed by the noise induced by the normal operation of the chip components.